74LS73 Dual JK Flip-Flop with Clear IC DIP-14 Package

The 74LS73 Dual JK Flip-Flop  is a dual negative-edge-triggered J-K flip-flop from Texas Instruments, featuring a master-slave configuration with complementary outputs. This device contains two independent flip-flops, with each flip-flop being triggered on the falling edge of the clock pulse. 74LS73 Dual JK Flip-Flop  allow the J and K inputs to change during both the HIGH and LOW phases of the clock without affecting the output, provided the setup and hold times are respected.

Note:

1. Product Images are shown for illustrative purposes only and may differ from the actual product.
2. For Technical Specifications about the IC go through the Datasheet in the Attachment section.
   

Features :

1. Propagation Delay Time: 20 ns
2. High Level Output Current: – 0.4 mA
3. Low Level Output Current: 8 mA
4. Number of Channels: 2
5. Operating Temperature Range: 0°C to +70°C

Package Includes:

1 x 774LS73 ,653 – Dual JK Flip-Flop Set/Reset Negative-edge Trigger IC DIp-14 Package